Electronic devices, such as computers, smart phones and the like, may use frequency synthesizers to generate clock signals that control various functions. For example, devices such as smart phones and notebook computers may use separate 25 MHz and 32 kHz crystal oscillators for communications and real time clock (RTC) functions, respectively. Such an arrangement may be expensive and use an undesirable amount of space. Some devices use a phase-locked loop (PLL) to generate a relatively low-frequency clock signal clock signal (e.g., ˜30 kHz) for RTC applications from a relatively high-frequency clock signal (e.g., ˜25 MHz) used for communications circuitry. Such conventional PLL-based approaches may, however, utilize relatively inefficient circuitry and, thus, may reduce battery life.